1. Technical Field
The present invention relates to a semiconductor wafer, a method of producing a semiconductor wafer and a heterojunction bipolar transistor.
2. Related Art
Group III-V compound semiconductor devices such as heterojunction bipolar transistors may have a connection region made of a semiconductor between the semiconductor region providing the operable region and the metal electrode to electrically connect them together. Such a semiconductor connection region preferably forms an ohmic contact with the metal electrode and has low contact resistance. In addition, the connection region itself preferably has low electrical resistance. For this reason, the semiconductor used to form the connection region is often a narrow band-gap semiconductor doped with a large amount of impurity atoms.
For example, when a heterojunction bipolar transistor has a collector made of n-type GaAs, a base made of p-type GaAs, an emitter made of n-type InGaP, and a sub-emitter made of n-type GaAs, a contact layer made of n-type InGaAs is formed between the emitter electrode made of metals and the sub-emitter as the above-described semiconductor connection region. Japanese Patent Application Publication No. 7-22327 discloses in Paragraphs [0002] to [0006] the problems caused by the use of the n-type InGaAs layer as the connection region and exemplary solutions for the problems.
Specifically speaking, Japanese Patent Application Publication No. 7-22327 discloses as follows.
“In the conventional art, . . . N+-type InyGa1-yAs crystal layer 3 is further vapor-deposited on element body 2, which provides the operable region (the collector, base, emitter and the like), and the crystal layer 3 is used as a non-alloy resistance contact region . . . . The N+-type InyGa1-yAs crystal layers 3 and 4 are typically formed by metal organic chemical vapor deposition (MOCVD). In this case, the dopant materials to be used typically include disilane (Si2H6) or monosilane (SiH4).”
“When the N+-type InyGa1-yAs crystal layer is used as a non-alloy resistance contact region . . . , the indium ratio y is typically at least set to 0.5 or higher. Here, in order to vapor-deposit InGaAs crystal layers having such an indium ratio, . . . the suitable temperature is 400° C. to 500° C., which is relatively low. On the other hand, the dopant materials of disilane and monosilane are highly efficiently implanted within a temperature range of 600° C. to 800° C., which is suitable for the vapor-deposition of GaAs crystal layers and AlGaAs layers, but significantly poorly implanted within the temperature range that is suitable for the vapor-deposition of InGaAs crystal layers.”
“Therefore, in order to perform heavy doping targeting a concentration of approximately 5×1019 cm−3, which is required to form non-alloy resistance contact layer . . . , with the use of disilane or monosilane as the dopant materials within the temperature range of 400° C. to 500° C., which is suitable for the vapor-deposition of InGaAs crystal, the source gas need to be pumped into the growth chamber at the concentration that is 10 to 100 times as high as the concentration employed for the vapor-deposition of GaAs crystal and AlGaAs crystal. When the source gas is fed at such a high concentration, however, the dopant materials themselves and silicon resulting from thermal decomposition of the dopant materials contaminate the growth chamber. Thus, it is difficult to grow highly pure crystal.
“The present invention aims to manufacture compound semiconductor devices having improved performances and to prevent the contamination of the growth chamber used to manufacture the compound semiconductor devices, by utilizing dopant materials that can be highly efficiently implanted at temperatures suitable for vapor-deposition of InGaAs and InAs crystal layers.”
“The above-described problems can be solved by using selenium as the dopant (donor impurity).”
“Selenium is a Group-VI element and serves as a donor impurity. In addition, selenium is always stable at relatively low temperatures suitable for vapor-deposition of InGaAs crystal layers or InAs crystal layers and the activation rate of selenium never degrades.”
Japanese Patent Application Publication No. 7-321058 also discloses in claim 4 that selenium may be used as the n-type dopant in place of silicon.
As disclosed in Japanese Patent Application Publications Nos. 7-22327 and 7-321058, the use of Group-VI atoms such as selenium as the n-type dopant can allow the n-type impurity atoms to be implanted at high concentration into InGaAs, which inevitably requires to be grown at low temperatures.
When Group-VI atoms such as selenium are used as the n-type dopant for InGaAs, however, the Group-VI atoms such as selenium remain within the epitaxial growth chamber and may unfavorably contaminate a next semiconductor wafer while it is being manufactured. In addition, the Group-VI atoms such as selenium have higher diffusion coefficient in solids than silicon. The atoms such as selenium may diffuse into the underlying layers during the epitaxial growth and compromise the reliability of the devices to be manufactured with the layers.
For the above-described reasons, it is preferable to use silicon atoms in place of Group-VI atoms such as selenium, as the n-type dopant for InGaAs crystal. When silicon atoms are used as the dopant, however, sufficient electrical conductivity cannot be achieved unless a large amount of silicon atoms are implanted as disclosed in Japanese Patent Application Publication No. 7-22327. The implantation of a large amount of silicon atoms degrades the crystallinity of InGaAs crystal and thus is not preferable.
The objective of the present invention is to provide a technique that can impart sufficient electrical conductivity to semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Another objective of the present invention is to provide a technique that can enhance the purity and crystallinity of semiconductor crystal by implanting a smaller amount of silicon atoms into the semiconductor crystal and thus provide n-type compound semiconductor crystal with low resistance and excellent crystallinity.